SRAM (static random access memory) memory devices are well known in the computer arts and usage is commonplace. SRAM may be Synchronous, i.e. clocked by edges of a clock, typically a master clock. In particular, in Synchronous SRAM, Addresses may be strobed at a rising clock edge and subject to customary set-up and hold constraints.
From a memory device (chip) user's perspective, various architectures are available and there are various trade-offs to take into account when selecting the memory architecture to use. For example, flow-through SRAM devices may present read-data one clock cycle after the memory address is presented. Pipelined SRAM devices may typically present read-data two clock cycles after the memory address is presented.
Std. Sync (standard synchronous) SRAM devices may typically expect simultaneous presentation of addresses and corresponding write-data at the same clock edge. “Single Late-Write” SRAM devices may typically expect write-data to be presented one clock cycle after the corresponding address is presented. NoBL™ (“No Bus Latency™”) SRAM devices may typically expect write-data to be presented two clock cycles after the corresponding address is presented. Burst modes are also used so that a single address setup and hold may initiate the transfer of multiple consecutively addressed words of data.
These various architectures have associated trade-offs. Trade-offs may include price, clock speed, read-write turnaround times, latency, circuit complexity and more. NoBL™ SRAMs may have advantages where latency is an important consideration by reducing or eliminating deselect cycles. Std. Sync SRAM devices may be particularly attractive in caching applications, such as where price and read-speed are the dominant factors.
Also there are legacy considerations, both supplier and user become invested, over time, in various ways and in particular interfaces, thus, there can be strong incentives to provide improved but compatible devices.
FIG. 1 shows a block diagram of part of the write-data circuit of a conventional Std. Sync. SRAM. Write-data may be presented at an external I/O pad 101, and clocked into a Master/Slave register 102. The data may then travel down on-chip data-in (di) lines 103 which, for example, may typically be about 6000 microns long. A write-driver circuit 104 may then transfer the data to the memory core 120 responsive to a write pulse signal (wps) from a delay circuit 105. The paths corresponding to time delays tD1, tD2 are discussed below, in connection with FIG. 3. As is conventional in similar block diagrams, only a single data or address line may be shown but the presence of multiple lines and signals in parallel may be inferred or assumed wherever relevant or apparent as is well-known in the art.
FIG. 2 shows a block diagram of part of a conventional Std. Sync. SRAM circuit. As contrasted with FIG. 1, it shows additional parts of what may be the same type of device, including part of a read-data circuit and an address circuit. In addition to the features of FIG. 1 there is an Address-Pad 201 to receive addresses (encoded as voltages) from off-chip and wherefrom they may be clocked into to Address Register 208 and thence to address decoder 209 for address selection in memory core 120. Also shown are data-out lines (do) 203 which convey read-data from the memory core 120 through write driver 104 to a pipeline register 202 and thence to I/O pad 101. The data-in lines 103 (di) switch (i.e. experience data-dependent transitions or non-transitions) even during read cycles. The paths corresponding to time delays tD1, tD2 are discussed below, in connection with FIG. 3.
FIG. 3 shows a timing diagram for a conventional SRAM, such as that of the device partially represented by FIGS. 1 and 2. It can be seen that Address and corresponding Write-Data (e.g. A0/D0) are presented effectively simultaneously. Time tD1 is equivalent to the time for data to travel from I/O pad 101 to registers 102, 208 (FIG. 1 or FIG. 2). More precisely, time tD1 is equivalent to the time to become stabilized rather than marginal or meta-stable, at the input to the registers 102, 208 (FIG. 1 or FIG. 2) responsive to a voltage transition. Time tD2 may be equivalent to the time for data to travel down the on chip data-in lines (di) 103 (FIG. 1 or FIG. 2). Time tW represents the time for the Write operation into the memory core and tR the time for Write recovery of the memory core. Other signals in FIG. 3 such as ck (data and address clock) and wps (write-pulse) are conventional in the art.
Still referring to FIG. 3 the master clock xclk is shown operating to generate timing signals W at the highest allowed frequency which is the inverse of the sum of the serially sequenced activity times, i.e. tCYCW(min)=tD1+tD2+tW+tR and f(max)=1/tCYCW(min) (seconds and Hz respectively). Thus, this configuration of SRAM provides early-write at the external interface and actually performs an early-write (as contrasted with, for example, NoBL™ devices (which may be characterized as double late-write)). SRAMs of this kind may be said to have an external interface according to static random access memory standard synchronous timings for early-write (or Std. Sync SRAM for short).